Resilient Cache Design for Mobile Processors in the Near-Threshold Regime
Near-threshold computing embodies an intriguing choice for extending mobile processor battery life due to its high energy efficiency. However, process, voltage and temperature variations cause a significantly high failure rate of level 1 cache SRAM cells in the near-threshold regime
compared to the super-threshold regime. In this work, we show that faulty cells in the near-threshold regime are highly clustered in certain regions of the cache. We then propose a low overhead technique to dynamically reduce the performance penalty due to process variations by exploiting
the spatial congregation of faulty cells and application cache behaviors. Our experimental results demonstrate up to 78% reduction in performance loss over two state-of-art techniques.
Keywords: FAULT TOLERANT CACHE; NEAR-THRESHOLD COMPUTING; SRAM RELIABILITY; VOLTAGE SCALING
Document Type: Research Article
Publication date: 01 June 2015
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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