Power-Aware Automated Pipelining of Combinational Circuits

Pipelining of combinational circuits with power, area and clock frequency constraints is a very useful way to increase operational speed of circuits. We solve the pipelining problem as a special case of retiming problem combining the effects of area-timing-power trade-off using gate sizing. For design constraints of area, power and gate sizing range, we give heuristic methods to attain pipelining close to optimal power aware minimum latency pipelined circuit. In this paper we formulate this problem as a Mixed Integer Non Linear Programming (MINLP) problem and we provide two heuristic methods to obtain good solutions. The first method is sensitivity based approach which gives good solution to circuits with large number of gates. The second method uses geometric programming method which is slower on large circuits, but works well for smaller designs. The two algorithms are tested on ISCAS-85 benchmark and circuits generated by our tool and compared for speed and efficiency. We study the varying impact of supply, threshold voltage and logic depth per pipeline stage on pipelining efficiency in terms of latency and total power consumption. We extend this method to show power reduction due to supply and threshold voltage scaling and find effective logic depth by varying logic depth per pipelining stage. Simulation work with 130 nm static CMOS model on benchmark circuits show that the effective logic depth per pipeline stage varies considerably for different supply and threshold voltage of the circuit. We find power efficient pipelined designs to operate best at low threshold voltage. Keeping the design constraints fixed, we obsere from our simulations that pipelined designs at certain threshold and supply voltage gives power savings of 10–85% compared to supply and threshold voltage that yield worse power cost. With design constraints fixed except logic depth and at fixed supply and threshold voltage we observe that pipelined design at effective logic depth has 10–60% savings in power cost compared to pipelined design at logic depth over a range of 4–22 FO4 delay.