Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter
In this paper, we propose a low energy consumption and area efficient successive approximation register analogue-to-digital converter. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array in comparison to other
nonbinary capacitor array based successive approximation register analogue-to-digital converters. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process
by balancing the parasitics at charge sharing nodes inside capacitor array, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time.
Keywords: AREA EFFICIENT ADC; DUAL CAPACITOR ARRAY; LOW ENERGY; NONBINARY CAPACITOR; SUCCESSIVE APPROXIMATION REGISTER ADC; UNIT CAPACITOR ARRAY
Document Type: Research Article
Publication date: 01 September 2015
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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