VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder
This paper proposes a un-grouped-sliding-window-technique (UGSWT) and a state metric normalization technique for logarithmic-maximum-a-posteriori-probability (LOG-MAP) algorithm. We have suggested a decoder architecture based on these techniques for high throughput application. Application-specific-integrated-circuit
(ASIC) implementation of the proposed decoder is carried out in 90 nm complementary-metal-oxide-semiconductor (CMOS) process and it has achieved a throughput of 612 Mbps at a maximum clock frequency of 625 MHz with an energy efficiency of 0.1 nJ/bit. Functional verification of the implemented
channel decoder is carried out using field-programmable gate-array (FPGA) which is interconnected with logic analyzer via high-speed-data-transfer card. Bit-error-rate (BER) performance of the implemented decoder has shown a coding loss of approximately 0.2 dB in comparison with the simulated
BER values.
Keywords: BER PERFORMANCE; FPGA; LOG-MAP ALGORITHM; SLIDING WINDOW TECHNIQUE; TURBO CODE; VLSI DESIGN
Document Type: Research Article
Publication date: 01 September 2015
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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