Chip Multiprocessor Performance Modeling for Contention Aware Task Migration and Frequency Scaling

Workload consolidation is usually performed in datacenters to improve server utilization for higher energy efficiency. One of the key issues in workload consolidation is the contention for shared resources. Dynamic voltage and frequency scaling (DVFS) of CPU is another effective technique that has been widely used to trade performance for power reduction. We have found that the degree of resource contention of a system affects its performance sensitivity to CPU frequency. Without detailed architecture level information, the complex relationship between contention, frequency and performance cannot be retrieved analytically. In this paper, we apply machine learning techniques to construct a model for chip multiprocessor (CMP) Performance Estimation under Fixed workload Scheduling (PEFS). It quantifies performance degradation of target process caused by resource contention and frequency scaling for current CMP workload with the assumption of a fixed task mapping. The model is further generalized for performance prediction with task migration (PPTM), which predicts the performance degradation after potential intra-processor task migration. Both models are tested on an SMT-enabled chip multi-processor with 10∼20% estimation error on average. Experimental results show that our PEFS model can keep the performance of those bottleneck tasks much closer to the performance threshold than all other techniques, which leads to almost no performance violation while achieves more energy savings, and task migration guided by our PPTM model produces 4%∼9% higher performance than conventional task migration guided by last level cache miss.