Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL

This paper illustrates low power design of delay flip-flop as it is implemented by a controlling clock signal which is a major source of power dissipation in sequential circuits. In digital circuits, delay flip-flops sense the input data, store and reflect it at the output to get processed by other elements synchronously or asynchronously. Scaling is undertaken to increase the packaging density in VLSI circuits which causes planar devices like flip-flops an adverse Short Channel Effect that needs to be minimized. So, in the proposed circuit conventional delay flip-flop, is implemented using Fin-type-Field-Effect Transistors (FinFET's) which are capable enough to reduce the slope of sub-threshold leakage and decrease the leakage power by suitable fin thickness and geometry. Parameter variation and noise analysis also reveal that FinFETs are suitable for flip-flop design as compared to MOSFET. We have considered a method for enriching the effectiveness of FinFETs by dropping the supply voltage and elevating the ground voltage value of the flip-flop circuit in standby mode. A comparative analysis has been done on Shorted Gate FinFETs based Delay flip-flop and Adaptive Voltage Level Shorted Gate FinFETs based Delay flip-flop over the same simulation conditions in Cadence Virtuoso Tool at 45 nm technology including temperature variations in AVL design. Simulation results depict a tremendous reduction of nearly 33.9% leakage power at 0.7 volt supply.