ARTL-Based Hardware Synthesis to Non-Heterogeneous Standard Cell ASIC Technologies

Register-Transfer Level (RTL) modeling and synthesis is a crucial part of digital system design. The constantly growing complexities of today's data processing systems make it more and more complicated to manage the RTL intent, timing, resource requirement and power-consumption of the macrocells in complex System-on-Chips (SoCs). Although there are numerous applications where the rapid prototyping is the primary objective; therefore, high level synthesis methods may be used to handle complexity and reduce design time but in case of highly timing-critical, resource-critical and/or power-consumption-critical applications the hand-crafted RTL design and time-consuming optimization is unavoidable. In this paper a new extension to RTL design and a specific synthesis method are introduced, which make a reduced design time achievable while supporting low-level micro-architectural optimization. The results of the investigations for design and synthesis efficiency are also presented with respect to the non-heterogeneous standard cell ASIC technologies.