Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip

High power dissipation in scan-based Logic-BIST testing is a vital issue. Low power approaches to handle all power problems of Logic-BIST have been proposed in our prior works, in which the toggle rate (switching activity) during the test operation (scan and capture) is well controlled. While significant reduction of the toggle rate has been confirmed, the amount of power reduction on a real chip is not known yet. In this paper, we implement the low power approaches on a Test Element Group (TEG) chip to investigate the physical effects of the low power scheme on a real chip in terms of current dissipation, voltage-drop and delay variations. Experimental results confirm the effectiveness of the low power scheme and show strong correlation between the simulated toggle rate and the measured (current, voltage-drop and delay variation) values. They show that the simulated toggle rate can be used as a good indicator of test power in test generation or design. The measured results of the actual power reduction caused by the toggle rate reduction should be valuable references to the low power test design.