Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors
A low voltage and low power SR-latch based flip-flop design is proposed. It is adapted from a classic text-book-style all-NAND based flip-flop design and achieves circuit simplification by eliminating redundant logic. The optimization measure leads to a new design featuring better timing
and power performance. The area and the power-delay-product of the proposed design also outperform those of the widely used transmission gate based flip-flop design significantly. The proposed design is further extended to a 6-bit Johnson counter using the TSMC 0.18 μm CMOS technology.
When operating in the nominal condition, i.e., (0.5 V/1 MHz), the design has a measured power consumption of 21.57 nW. For the target 1 MHz working frequency, the required VDD
can be even reduced to 0.402 V and the power consumption is less than 10 nW.
Keywords: FLIP-FLOP; LOW POWER; LOW VOLTAGE; PASS-TRANSISTOR LOGIC; SR-LATCH
Document Type: Research Article
Publication date: 01 June 2016
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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