Design of 8T Volatile and Non-Volatile RAM Cells with Improved Holding Phase Performance

In this study curtailing of idle current using 8T volatile and non-volatile (memristor-based) DRAM cells by exploiting body effect in the access transistors and footing the storage transistor is proposed. The dual technique implemented increase threshold voltage of the two access transistor through increasing source to bulk voltage and creating virtual ground on the storage transistor during the holding phase of DRAM cells. The modern large memory arrays endure prolonged idle periods which entail that more idle leakage current and power is experienced leading to increased overall power dissipation and also the holding time of volatile cells decreases thereby increasing refreshing power. The dual techniques postulated in this paper reduce the idle current which in-turn improves the holding phase performance of the arrays. The proposed techniques were implemented and simulations were done at 45 nm technology using Cadence virtuoso tool. The methods improved the leakage current, holding time and leakage power but at the expense of area and writing power.