Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies

Energy efficiency has been a primary focus over the past decade. Energy saving techniques such as dynamic voltage and frequency scaling, power gating, and many-core systems-on-chip, have been extensively studied. These techniques, however, struggle to deliver desired energy efficiencies while failing to exploit wide supply voltage ranges in mobile sub-22 nm microprocessors. Additionally, scaling exacerbates these problems, resulting in significant parasitic interconnect resistances. A major factor that limits dynamic wide voltage ranges and frequency scaling is the inability to optimize interconnect to support a wide voltage range from nominal to subthreshold voltages. The primary contribution of this work is the analysis and optimization of repeater insertion for wide supply voltage range applications. A closed-form delay model supporting wide voltage ranges is developed to enable this analysis. The model supports an ultra-wide voltage range from nominal voltages to deep subthreshold voltages, and repeater size multipliers up to 640 times the minimal size. The model is validated with SPICE using a commercial 14 nm FinFET transistor model for interconnect resistances and capacitances up to, respectively, 2 kΩ and 2 pF. The model exhibits good accuracy across the entire parameter space, with the worst case error ranging from –3.5% to 7.3% (–12% to 13% in the subthreshold region) for single stage delays, and from –17% to 9% (–15% to 17% in the subthreshold region) for long interconnect lines with repeaters. Challenges to repeater insertion are also evaluated based on the proposed model.