Prospects of 2D Junctionless Channel Transistor (JLCT) Towards Analog and RF Metrics Using Si and SiGe in Device Layer
In this paper, we propose an interpretation of the junctionless (JL) 2D FinFET for achieving improved analog/RF metrics as compared to conventional architecture. The simulation study shows performance improvement in term of voltage gain (AV
) and cut-off frequency (fT
).
In this structure, the merits of device layer with Silicon–Germanium (Si1–0.25Ge0.25) along with Silicon (Si) materials as a channel are studied. The results would serve as a worthy design tool for low power and high performance CMOS circuits.
Keywords: 2D-FINFET; ANALOG AND RF; CUT-OFF FREQUENCY; GENERATION FACTOR; ION–IOFF; JUNCTIONLESS TRANSISTORS; SI1–0.25GE0.25 DEVICE LAYER; TRANSCONDUCTANCE
Document Type: Research Article
Publication date: 01 September 2017
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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