A 12-Bit Ultra-Low Voltage Noise Shaping Successive-Approximation Register Analogto-Digital Converter Using Emerging TFETs

This paper presents an energy efficient 12-bit noise shaping (NS) successive-approximation register (SAR) analog-to-digital converter (ADC). The 2nd-order noise shaping architecture with multiple feedforward paths is adopted and analyzed to optimize system design parameters. By utilizing tunnel field effect transistors (TFETs), the Δ∑ SAR is realized under an ultra-low supply voltage VDD with high energy efficiency. A fully-differential Δ∑ SAR ADC using 20 nm TFET technology is designed and evaluated. At a 0.3 V supply voltage and 1.38 MHz sampling rate of oversampling ratio (OSR), the proposed ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 71.98 dB and a corresponding effective number of bits (ENOB) of 11.64 bits and power consumption of 0.94 μW which result in the Schreier figure of merit of 178.7 dB.