An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization

In nano-CMOS circuit, leakage power plays an important role to overall power dissipation of the circuit. In the present work, we develop some techniques for reducing the leakage power during post-physical-optimization process. It uses TED (Taylor Expansion Diagram) for generating optimized DFG (Data Flow Graph) of the given netlist. Once DFG is obtained, it finds out interconnects which plays critical role to determine the speed of the design. It then optimizes those interconnects by using different techniques such as inserting repeaters, sizing the net segments, etc. After modeling interconnects, it updates the DFG with inserted repeaters and delay of the wire segments. It then selectively binds non-critical components to corresponding functional unit consisting of transistors of high oxide thickness and critical components with low oxide thickness. As the algorithm considers time-constraint explicitly, it reduces leakage current without degrading the performance of the design. Experimental results on a set of different industrial designs show 18% to 35% reduction in leakage current compared to the results obtained by a conventional optimization flow.