Performance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices

In this paper, the performance tradeoffs of three different SRAM arrays of size 1 K × 16 with power reductions techniques are investigated for implantable devices. The three SRAM arrays investigated consists of 6, 7 and 8 transistors in each 1-bit memory cell. The low power techniques applied to these SRAM arrays are power gating technique, data retention voltage and use of high threshold transistors. First, these leakage power reduction techniques are applied independently to the SRAM arrays and then applied simultaneously to determine the tradeoffs in the power-performance. The SRAM arrays are investigated using 16 nm and 22 nm bulk CMOS transistor models and using 10 nm, 14 nm, 16 nm and 20 nm FinFET transistor models. Leakage power, read delay, write delay and power delay products are measured and analyzed. For SRAM arrays using bulk CMOS transistors, it was determined that the use of high threshold transistors and power gating technique simultaneously could only save less than 4% of leakage power as compared to using the power gating technique only in 22 nm technology node and no savings in 16 nm technology node. Use of power gating technique and data retention voltage in FinFET technology nodes saved more than 95% of leakage. Use of data retention voltage was effective in reducing the leakage power for all the arrays investigated in this research. The 6T SRAM cell based memory array using high threshold transistors exhibited the lowest power delay product without power gating. 20 nm FinFET nodes exhibited the lowest power delay product among the three SRAM arrays analyzed.