A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI
This paper describes a solution for SOC 'on-chip sensor' management exploiting the robustness of delay insensitive clockless logic. This low signal count, high bandwidth and variation insensitive solution, provides SOC architects a means to integrate on chip sensors (e.g., process monitor
sensors), with a simplification of design integration and verification requirements. This is demonstrated by silicon measurements accessing sensors across the network for an ultra-wide voltage range 0.4 V–1.3 V.
Keywords: ASYNCHRONOUS LOGIC; DELAY INSENSITIVE; FDSOI; PROCESS MONITORING; SENSOR NETWORK; SYSTEM ON CHIPS
Document Type: Research Article
Publication date: 01 September 2018
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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