Low Swing Charge Recycling Driver for On-Chip Interconnect
This paper reviews a number of single voltage supply driver schemes for the on-chip parallel buses in the deep sub-micron CMOS technology, and presents the comprehensive efficiency analysis of delay, and energy that are affected by the coupling capacitance. In addition, we present a
new charge recycling (CR) driver scheme structure that achieves a better energy-delay product reduction when connected to a long interconnect line. The performance of each scheme is thoroughly examined using the HSPICE simulation on the benchmark bus circuits. The paper also performs a noise
analysis for each schemes. For specific UMC 65 nm CMOS technology, we present a solution which can reduce energy-delay product beyond 15% for interconnect lines longer than 2 mm.
Keywords: CHARGE RECYCLING TECHNIQUE; CMOS; DRIVER; INTERCONNECT LINE; LOW POWER; LOW THRESHOLD VOLTAGE
Document Type: Research Article
Publication date: 01 September 2018
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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