Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power

This paper presents the design and evaluation of the proposed Clocked CMOS Differential Adiabatic Logic (CCDAL), a two-phase clock operated charge recovery logic. The evaluation of the logic is made through implementation of an 8-bit Carry Save multiplier circuit operated using two complementary sinusoidal power clock signals. The proposed logic circuit inherits all the advantages of Clocked CMOS Adiabatic Logic (CCAL) and further exhibits improved drivability and circuit robustness resulting in higher frequency performance even while operating at low power. The adiabatic multiplier has been verified upto a maximum operating frequency of 500 MHz. Extensive simulations support the claim that proposed multiplier is energy efficient at high frequencies compared to other two-phase adiabatic counterparts, namely, Quasi Static Energy Recovery Logic (QSERL) and Two-phase Adiabatic Dynamic Logic (2PADL) and Clocked CMOS Adiabatic Logic (CAL). The multiplier is designed using 180 nm technology library and simulations are carried out using industry standard Cadence^® Virtuoso tool.