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Sohaib Majzoub ; Mottaqiallah Taouil ; Said Hamdioui
System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation
2019-05-10T08:09:50Z
2019-10-01T11:22:39+02:00
2019-10-01T11:22:39+02:00
LOW-POWER DESIGN ; SYSTEM-LEVEL MODELLING ; PLANAR CMOS ; FINFET ; PROCESS VARIATION ; WITHIN-DIE VARIATION ; ALPHA-POWER MODEL ; MULTI- VDD ; VOLTAGE SCALING
iText 2.1.7 by 1T3XT
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