3D layout of the Spidergon-Donut on-chip interconnection network
by Fadi N. Sibai; Abu Asaduzzaman; Ali Elmoursy
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 11, No. 3, 2023

Abstract: 3D integration promises to resolve many of the heat and die size limitations of 2D integrated circuits. A critical step in the design of 3D many-cores and MPSOCs is the layout of their 3D network-on-chip (NoC). In this paper, we explore and present multiple 3D layouts of the Spidergon-Donut (SD) NoC and estimate their longest wire lengths and cost requirements. For a total of 64 cores, the 4×2×8 and 2×4×8 placements result in the best longest wire delays, with the former higher 3D integration costs, while the second requiring larger chip area and through-silicon-vias (TSV) array costs. Such study helps in guiding 3D integration direction and weighing 3D NoC layout and placement alternatives.

Online publication date: Thu, 06-Apr-2023

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