Abstract
Resistive Random Access Memory (RRAM), also termed as memristors, is a non-volatile memory where information is stored in memory cells in the form of resistance. Due to its non-volatile resistive switching properties, memristors, in the form of crossbars, are used for storing information, neuromorpic computing, and logic synthesis. In spite of the wide range of applications, memristive crossbars suffer from a so-called sneak path problem which results in an erroneous reading of memristor’s state. Till date, no or very few logic synthesis approaches for in-memory computing have considered the sneak path problem during the realizations of Boolean functions. In other words, the effects of sneak paths on the Boolean function realizations in crossbars still remain an open problem. In this paper, we have addressed this issue. In particular, we study the impacts of function realizations in two memristive crossbar structures: Zero-Transistor-One-Resistor (0T1R) and One-Transistor-One-Resistor (1T1R) in the presence of sneak paths. Experimental analysis on IWLS and ISCAS-85 benchmarks shows that even in the presence of sneak paths, the 1T1R crossbar structures with multiple rows and columns are the most efficient as compared to the 1T1R structures with single row and multiple columns in terms of crossbar size and number of execution cycles.
About the authors
Dr. Kamalika Datta completed her Master of Science (MS) from Indian Institute of Technology Kharagpur, India in 2010, and PhD from Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India in 2014. She joined the National Institute of Technology Meghalaya, India as an Assistant Professor in the Department of Computer Science and Engineering in the year 2014. She is presently working as a Senior Researcher at the Deutsches Forschungszentrum fur Kunstliche Intelligenz (DFKI) Bremen, Germany. She has published more than 80 papers in peer reviewed journals and conferences. Her research interests include logic design using emerging technologies, synthesis and optimization of reversible and quantum circuit, and embedded systems.
Dr. Arighna Deb received the PhD (Engineering) degree from Jadavpur University, Kolkata, India, in 2017, and the Dr.rer.nat. degree from the University of Bremen, Bremen, Germany, in 2018. He is currently an Assistant Professor with the School of Electronics Engineering, KIIT University, Bhubaneswar, India. His research interests include the logic synthesis for conventional technologies and emerging technologies, such as quantum computing, optical computing, and in-memory computing.
Dr. Abhoy Kole received the MTech degree in information and Communication Technology in 2015, and the PhD degree in 2021, both from the Indian Institute of Technology Kharagpur, India. He joined the German Research Center for Artificial Intelligence, DFKI Bremen, Germany as a Post-Doctoral Researcher in the year 2022. His current research interests include resistive in-memory computing, reversible and quantum computing, and synthesis and optimization of quantum circuits.
Prof. Dr. Rolf Drechsler received the Diploma and Dr. Phil. Nat. degrees in computer science from J.W. Goethe University Frankfurt am Main, Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and with the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since October 2001, he has been with the University of Bremen, Bremen, Germany, where he is currently a Full Professor and the Head of the Group for Computer Architecture, Institute of Computer Science. In 2011, he additionally became the Director of the Cyber-Physical Systems group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. Rolf Drechsler was a member of Program Committees of numerous conferences including e.g. DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, FMCAD, Symposiums Chair ISMVL 1999 and 2014, Symposium Chair ETS 2018, and the Topic Chair for “Formal Verification” DATE 2004, DATE 2005, DAC 2010, as well as DAC 2011. He received best paper awards at HVC in 2006, FDL in 2007 and 2010, DDECS in 2010 and ICCAD in 2013 and 2018. He is an Associate Editor of TCAD, JETC, and further journals. He is an ACM Distinguished Member and an IEEE Fellow.
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Author contributions: All the authors have accepted responsibility for the entire content of this submitted manuscript and approved submission.
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Research funding: None declared.
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Conflict of interest statement: The authors declare no conflicts of interest regarding this article.
References
[1] W. M. Arden, “Challenges for the next 15 years,” Curr. Opin. Solid State Mater. Sci., vol. 6, no. 5, pp. 371–377, 2002.10.1016/S1359-0286(02)00116-XSearch in Google Scholar
[2] L. Chua, “Memristor – the missing circuit element,” IEEE Trans. Circuit Theor., vol. 18, no. 5, pp. 507–519, 1971. https://doi.org/10.1109/tct.1971.1083337.Search in Google Scholar
[3] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,” Nature, vol. 453, pp. 80–83, 2008. https://doi.org/10.1038/nature06932.Search in Google Scholar PubMed
[4] J. J. Yang, D. B. Strukov, and D. R. Stewart, “Memristive devices for computing,” Nat. Nanotechnol., vol. 8, nos. 13–24, pp. 13–24, 2013. https://doi.org/10.1038/nnano.2012.240.Search in Google Scholar PubMed
[5] S. Kvatinsky, D. Belousov, S. Liman, et al.., “MAGIC memristor-aided logic,” IEEE Trans. Circuits Syst. II, vol. 61, no. 11, pp. 895–899, 2014. https://doi.org/10.1109/tcsii.2014.2357292.Search in Google Scholar
[6] P. L. Thangkhiew, R. Gharpinde, and K. Datta, “Efficient mapping of boolean functions to memristor crossbar using magic nor gates,” IEEE Trans. Circuits Syst. I, vol. 65, no. 8, pp. 2466–2476, 2018. https://doi.org/10.1109/tcsi.2018.2792474.Search in Google Scholar
[7] R. Gharpinde, P. L. Thangkhiew, K. Datta, and I. Sengupta, “A scalable in-memory logic synthesis approach using memristor crossbar,” IEEE Trans. VLSI Syst., vol. 26, pp. 355–366, 2018. https://doi.org/10.1109/tvlsi.2017.2763171.Search in Google Scholar
[8] S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, and R. Drechsler, “Logic synthesis for rram-based in-memory computing,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 37, no. 7, pp. 1422–1435, 2018. https://doi.org/10.1109/tcad.2017.2750064.Search in Google Scholar
[9] R. Ben-Hur, R. Ronen, A. Haj-Ali, et al.., “Simpler magic: synthesis and mapping of in-memory logic executed in a single row to improve throughput,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 39, no. 10, pp. 2434–2447, 2020. https://doi.org/10.1109/tcad.2019.2931188.Search in Google Scholar
[10] D. N. Yadav, P. L. Thangkhiew, and K. Datta, “Look-ahead mapping of boolean functions in memristive crossbar array,” Integration, vol. 64, pp. 152–162, 2019. https://doi.org/10.1016/j.vlsi.2018.10.001.Search in Google Scholar
[11] S. P. Adhikari, C. Yang, H. Kim, and L. O. Chua, “Memristor bridge synapse-based neural network and its learning,” IEEE Trans. Neural Networks Learn. Syst., vol. 23, no. 9, pp. 1426–1435, 2012. https://doi.org/10.1109/tnnls.2012.2204770.Search in Google Scholar PubMed
[12] M. A. Zidan, H. A. H. Fahmy, M. M. Hussain, and K. N. Salama, “Memristor-based memory: the sneak paths problem and solutions,” Microelectron. J., vol. 44, pp. 176–183, 2013. https://doi.org/10.1016/j.mejo.2012.10.001.Search in Google Scholar
[13] F. Gul, “Addressing the sneak-path problem in crossbar RRAM devices using memristor-based one Schottky diode-one resistor array,” Results Phys., vol. 12, pp. 1091–1096, 2019, https://doi.org/10.1016/j.rinp.2018.12.092.Search in Google Scholar
[14] F. Lalchhandama, M. Sahani, V. M. Srinivas, I. Sengupta, and K. Datta, “In-memory computing on resistive ram systems using majority operation,” J. Circuits, Syst. Comput., vol. 31, no. 4, 2022, Art. no. 2250071. https://doi.org/10.1142/s0218126622500712.Search in Google Scholar
[15] C. Albrecht, “Iwls 2005 benchmarks,” in International Workshop for Logic Synthesis (IWLS), 2005. Available at: http://www.iwls.org.Search in Google Scholar
[16] M. C. Hansen, H. Yalcin, and J. P. Hayes, “Unveiling the iscas-85 benchmarks: a case study in reverse engineering,” IEEE Des. Test Comput., vol. 16, no. 3, pp. 72–80, 1999. https://doi.org/10.1109/54.785838.Search in Google Scholar
[17] K. Akarvardar and H. S. P. Wong, “Ultralow voltage crossbar nonvolatile memory based on energy-reversible NEM switches,” IEEE Electron. Device Lett., vol. 30, no. 6, pp. 626–628, 2009. https://doi.org/10.1109/led.2009.2018289.Search in Google Scholar
[18] E. Linn, R. Rosezin, C. Kugeler, and R. Waser, “Complementary resistive switches for passive nanocrossbar memories,” Nat. Mater., vol. 9, no. 5, pp. 403–406, 2010. https://doi.org/10.1038/nmat2748.Search in Google Scholar PubMed
[19] Y. Cassuto, S. Kvatinsky, and E. Yaakobi, “Sneak-path constraints in memristor crossbar arrays,” in Intl. Symp. on Information Theory, 2013, pp. 156–160.10.1109/ISIT.2013.6620207Search in Google Scholar
[20] A. Chen, “A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics,” IEEE Trans. Electron. Dev., vol. 60, no. 4, pp. 1318–1326, 2013. https://doi.org/10.1109/ted.2013.2246791.Search in Google Scholar
[21] M. A. Zidan, A. M. Eltawil, F. Kurdahi, H. A. H. Fahmy, and Khaled, “Memristor multiport readout: a closed-form solution for sneak paths,” IEEE Trans. Nanotechnol., vol. 13, pp. 274–282, 2014. https://doi.org/10.1109/tnano.2014.2299558.Search in Google Scholar
[22] Z. Tang, Y. Wang, Y. Chi, and L. Fang, “Comprehensive sensing current analysis and its guideline for the worst-case scenario of rram read operation,” Electronics, vol. 7, no. 10, pp. 1–13, 2018. https://doi.org/10.3390/electronics7100224.Search in Google Scholar
[23] R. Joshi and J. M. Acken, “Sneak path characterization in memristor crossbar circuits,” Int. J. Electronics, vol. 108, no. 8, pp. 1255–1272, 2021. https://doi.org/10.1080/00207217.2020.1843716.Search in Google Scholar
[24] E. Lehtonen and M. Laiho, “Stateful implication logic with memristors,” in Intl. Symposium on Nanoscale Arch., 2009, pp. 33–36.10.1109/NANOARCH.2009.5226356Search in Google Scholar
[25] S. Chakraborti, P. V. Chowdhary, K. Datta, and I. Sengupta, “BDD based synthesis of boolean functions using memristors,” in Proc. Intl. Design and Test Symp. (IDT), 2014, pp. 136–141.10.1109/IDT.2014.7038601Search in Google Scholar
[26] S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, and R. Drechsler, “Fast Logic Synthesis for RRAM-Based In-Memory Computing Using Majority-Inverter Graphs,” in 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 948–953.10.3850/9783981537079_0771Search in Google Scholar
[27] P. L. Thangkhiew, A. Zulehner, R. Wille, K. Datta, and I. Sengupta, “An efficient memristor crossbar architecture for mapping boolean functions using binary decision diagrams (BDD),” Integration, vol. 71, pp. 125–133, 2020. https://doi.org/10.1016/j.vlsi.2019.11.014.Search in Google Scholar
[28] L. Amaru, P.-E. Gaillardon, and G. D. Micheli, “Majority inverter graph: a novel data-structure and algorithms for efficient logic optimization,” in Design Automation Conf., 2014, pp. 1–6.10.1145/2593069.2593158Search in Google Scholar
[29] S. Shirinzadeh, M. Soeken, P. E. Gaillardon, and R. Drechsler, “Logic synthesis for majority based in-memory computing,” in Memristors, Memristive Devices and Systems, Springer, 2017, pp. 425–448.10.1007/978-3-319-51724-7_17Search in Google Scholar
[30] M. Soeken, P. E. Gaillardon, S. Shirinzade, R. Drechsler, and G. De Micheli, A PLiM Computer for the IoT. Computer, vol. 50, 6th ed. IEEE, 2017, pp. 32–37.10.1109/MC.2017.173Search in Google Scholar
[31] S. Shirinzadeh, M. Soeken, P. E. Gaillardon, G. De Micheli, and R. Drechsler, “Endurance management for resistive logic-in-memory computing architectures,” in Design, Automation & Test in Europe, 2017, pp. 1092–1097. https://doi.org/10.23919/DATE.2017.7927152.Search in Google Scholar
[32] CIRKIT. Available at: https://github.com/msoeken/cirkit.Search in Google Scholar
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