This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The loop delay due to the D flip-flops at filter's output is compensated in order to lower the noise peak and stably achieve wide loop bandwidth. The input-referred jitter is lowered by using a successive-approximated-register analog-to-digital converter (SAR-ADC)-based sampling phase detector (SPD). A stacked reference buffer is introduced to reduce the transient short-circuit current for low power and low reference spur. The locking issue due to the steady-state phase error in a type-I PLL and the limited range of the phase detector is addressed using a TDC-assisted loop. The loop stability and phase noise are analyzed, suggesting a trade-off for the minimum jitter. The solutions in detail are described. The prototype PLL fabricated in 65 nm CMOS demonstrates 2.0 ps RMS jitter, 3.1 mW power consumption, and 0.067 mm² area, with 50 MHz reference frequency and 2.0 GHz output frequency.