CMOS SoCs can reduce power consumption by adopting voltage scaling (VS) technologies, where the level converter (LC) is required between voltage domains to avoid dc current. However, the LC often induces high delay penalty and usually results in non-balanced rise and fall delays. Therefore, the performance of the LC strongly affects the effectiveness of VS technologies. In this paper, heuristic sizing methodology for designing a state-of-the-art LC is developed and proposed. Using the proposed methodology, we can design the LC to achieve high performance with balanced rise and fall delay times in a deterministic way.