The minimum operating voltage, V_min, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate V_min. It shows that V_min is very sensitive to the lowest necessary threshold voltage, V_t0, of MOSFETs and to threshold-voltage variations, ΔV_t, which become more significant with device scaling. There is thus a need for low-V_t0 circuits and ΔV_t-immune MOSFETs to reduce V_min. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest V_min. Various techniques are thus proposed to reduce the V_min: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce V_min of other circuit blocks, dual-V_t0 and dual-V_DD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-V_t0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for V_t-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce V_min to less than 0.5V, if combined with the low-V_t0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.