An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology

Tetsuro MATSUNO; Daisuke FUJIMOTO; Daisuke KOSAKA; Naoyuki HAMANISHI; Ken TANABE; Masazumi SHIOCHI; Makoto NAGATA

doi:10.1587/transele.E93.C.820

Special Section on Analog Circuits and Related SoC Integration Technologies

An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology

Tetsuro MATSUNO, Daisuke FUJIMOTO, Daisuke KOSAKA, Naoyuki HAMANISHI, Ken TANABE, Masazumi SHIOCHI, Makoto NAGATA

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Keywords: noise emulation, substrate noise, power supply noise, signal integrity, substrate coupling, power integrity

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2010 Volume E93.C Issue 6 Pages 820-826

DOI https://doi.org/10.1587/transele.E93.C.820

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Abstract

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2mm² in a 65nm 1.2V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.

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