1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells

Shingo MANDAI; Tetsuya IIZUKA; Toru NAKURA; Makoto IKEDA; Kunihiro ASADA

doi:10.1587/transele.E94.C.1098

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1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells

Shingo MANDAI, Tetsuya IIZUKA, Toru NAKURA, Makoto IKEDA, Kunihiro ASADA

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Keywords: time-to-digital converter, TDC, time-difference-amplifier, TDA, time amp

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2011 Volume E94.C Issue 6 Pages 1098-1104

DOI https://doi.org/10.1587/transele.E94.C.1098

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Abstract

This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2ps time resolution over 1.3ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0ps time resolution over 60ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.

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