A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis

Chizu MATSUMOTO; Yuichi HAMAMURA; Yoshiyuki TSUNODA; Hiroshi UOZAKI; Isao MIYAZAKI; Shiro KAMOHARA; Yoshiyuki KANEKO; Kenji KANAMITSU

doi:10.1587/transele.E94.C.353

Regular Section

A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis

Chizu MATSUMOTO, Yuichi HAMAMURA, Yoshiyuki TSUNODA, Hiroshi UOZAKI, Isao MIYAZAKI, Shiro KAMOHARA, Yoshiyuki KANEKO, Kenji KANAMITSU

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Keywords: defects, failure analysis, fail bit signature, critical area analysis, integrated circuit layout

JOURNAL RESTRICTED ACCESS

2011 Volume E94.C Issue 3 Pages 353-360

DOI https://doi.org/10.1587/transele.E94.C.353

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Abstract

In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within ±0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65nm technology node products.

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