On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch

Jinmyoung KIM; Toru NAKURA; Hidehiro TAKATA; Koichiro ISHIBASHI; Makoto IKEDA; Kunihiro ASADA

doi:10.1587/transele.E94.C.511

Special Section on Circuits and Design Techniques for Advanced Large Scale Integration

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch

Jinmyoung KIM, Toru NAKURA, Hidehiro TAKATA, Koichiro ISHIBASHI, Makoto IKEDA, Kunihiro ASADA

Author information

Keywords: power supply noise, resonance, parasitic capacitance, sleep block, DVS, power gating

JOURNAL RESTRICTED ACCESS

2011 Volume E94.C Issue 4 Pages 511-519

DOI https://doi.org/10.1587/transele.E94.C.511

Details

Abstract

This paper presents an on-chip resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. The test chip was fabricated in a 0.18µm CMOS process and measurement results show 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. The proposed method requires 1.5% area overhead for four 100k-gate blocks, which is 7.1X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.

Corresponding author

Register with J-STAGE for free!