We have succeeded in fabricating 180nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔV_B. The ΔV_B, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53V to 0.69V, and threshold voltage of PMOS fluctuates in the range of -0.47V to -0.67V, the CC-MCML technique is able to suppress ΔV_B within only 30mV, where as the conventional MCML technique caused maximum ΔV_B of 1.0V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.