Based on a reverse converter algorithm derived from the New Chinese Remainder Theorem I, an algorithm for sign detection of RNS {2ⁿ-1, 2ⁿ, 2ⁿ+1} is presented in this paper. The hardware of proposed algorithm can be implemented using two n-bit additions and one (n+1)-bit comparator. Comparing with the previous paper, the proposed algorithm has reduced the number of additions used in the circuit. The experimental results show that the proposed circuit achieves 17.3% savings in area for small moduli and 10.5% savings in area for large moduli on an average, with almost the same speed. The power dissipations obtain 12.6% savings in average.