Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

Yoshitaka HIRAMATSU; Hasitha Muthumala WAIDYASOORIYA; Masanori HARIYAMA; Toru NOJIRI; Kunio UCHIYAMA; Michitaka KAMEYAMA

doi:10.1587/transele.E95.C.1872

Regular Section

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

Yoshitaka HIRAMATSU, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Toru NOJIRI, Kunio UCHIYAMA, Michitaka KAMEYAMA

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Keywords: block matching, heterogeneous multi-core, dynamically reconfigurable processor, data transfer, accelerator

JOURNAL RESTRICTED ACCESS

2012 Volume E95.C Issue 12 Pages 1872-1882

DOI https://doi.org/10.1587/transele.E95.C.1872

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Abstract

The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16×16 pixel blocks.

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