Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation

Takuya SAWADA; Taku TOSHIKAWA; Kumpei YOSHIKAWA; Hidehiro TAKATA; Koji NII; Makoto NAGATA

doi:10.1587/transele.E95.C.586

Special Section on Solid-State Circuit Design - Architecture, Circuit, Device and Design Methodology

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation

Takuya SAWADA, Taku TOSHIKAWA, Kumpei YOSHIKAWA, Hidehiro TAKATA, Koji NII, Makoto NAGATA

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Keywords: SRAM, Immunity, On chip monitoring, Built-in self testing

JOURNAL RESTRICTED ACCESS

2012 Volume E95.C Issue 4 Pages 586-593

DOI https://doi.org/10.1587/transele.E95.C.586

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Abstract

The susceptibility of a static random access memory (SRAM) core against static and dynamic variation of power supply voltage is evaluated, by using on-chip diagnosis structures of memory built-in self testing (MBIST) and on-chip voltage waveform monitoring (OCM). The SRAM core of interest in this paper is a synthesizable version applicable to general systems-on-a-chip (SoC) design, and fabricated in a 90nm CMOS technology. RF power injection to power supply networks is quantified by OCM. The number of resultant erroneous bits as well as their distribution in the cell array is given by MBIST. The frequency-dependent sensitivity reflects the highly capacitive nature of densely integrated SRAM cells.

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