On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction

Jinmyoung KIM; Toru NAKURA; Hidehiro TAKATA; Koichiro ISHIBASHI; Makoto IKEDA; Kunihiro ASADA

doi:10.1587/transele.E95.C.643

Special Section on Solid-State Circuit Design - Architecture, Circuit, Device and Design Methodology

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction

Jinmyoung KIM, Toru NAKURA, Hidehiro TAKATA, Koichiro ISHIBASHI, Makoto IKEDA, Kunihiro ASADA

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Keywords: resonant supply noise, switched parasitic capacitors, sleep block, power gating

JOURNAL RESTRICTED ACCESS

2012 Volume E95.C Issue 4 Pages 643-650

DOI https://doi.org/10.1587/transele.E95.C.643

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Abstract

Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2V, 65nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.

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