Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer

Jae Hwa SEO; Jae Sung LEE; Yun Soo PARK; Jung-Hee LEE; In Man KANG

doi:10.1587/transele.E96.C.644

Special Section on Fundamentals and Applications of Advanced Semiconductor Devices

Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer

Jae Hwa SEO, Jae Sung LEE, Yun Soo PARK, Jung-Hee LEE, In Man KANG

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Keywords: gate-all-around (GAA), tunneling field-effect transistor (TFET), tunneling-boost n-layer, hetero-gate dielectric

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2013 Volume E96.C Issue 5 Pages 644-648

DOI https://doi.org/10.1587/transele.E96.C.644

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Abstract

A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (I_on) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (L_high-k) for the fixed n-layer length (L_n-layer). The simulation results have been analyzed in terms of on- and off- current (I_on and I_off), subthreshold swing (SS), and RF performances.

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