This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70dB, SFDR of 79dB at nyquist input frequency in a 65nm CMOS process under 1.2V power supply voltage for 1.2Vp-p input signal swing. The estimated power consumption of the 12b 200MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6mW with a small FOM of 22fJ/conv-step.