This paper describes the design of an interpolated pipeline analog-to-digital converter (ADC). By introducing the interpolation technique into the conventional pipeline topology, it becomes possible to realize a more than 10-bits resolution and several hundred MS/s ADC using low-gain open-loop amplifiers without any multiplying digital-to-analog converter (MDAC) calibration. In this paper, linearity requirement of the amplifier is analyzed with the relation of reference range and stage resolution first. Noise characteristic is also discussed with amplifier's noise bandwidth and load capacitance. After that, sampling speed and SNR characteristic are examined with various amplifier currents. Next, the resolution optimization of the pipeline stage is discussed based on the power consumption. Through the analysis, reasonable parameters for the amplifier can be defined, such as transconductance, source degeneration resistance and load capacitance. Also, optimized operating speed and stage resolution for interpolated pipelined ADC is shown. The analysis in this paper is valuable to both the design of interpolated pipeline ADCs and other circuits which incorporate interpolation and amplifiers.