Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation

Satoshi TAKAYA; Yoji BANDO; Toru OHKAWA; Toshiharu TAKARAMOTO; Toshio YAMADA; Masaaki SOUDA; Shigetaka KUMASHIRO; Tohru MOGAMI; Makoto NAGATA

doi:10.1587/transele.E96.C.884

Special Section on Analog Circuits and Related SoC Integration Technologies

Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation

Satoshi TAKAYA, Yoji BANDO, Toru OHKAWA, Toshiharu TAKARAMOTO, Toshio YAMADA, Masaaki SOUDA, Shigetaka KUMASHIRO, Tohru MOGAMI, Makoto NAGATA

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Keywords: mixed signal VLSI circuit, substrate crosstalk, on-chip noise monitoring

JOURNAL RESTRICTED ACCESS

2013 Volume E96.C Issue 6 Pages 884-893

DOI https://doi.org/10.1587/transele.E96.C.884

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Abstract

The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.

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