Racetrack memory is a new type of high-capacity memory that stores data in magnetic nanowires called racetracks. Data is transferred through the nanowires to the access port for reading and writing. However, the data transfer process is imperfect and can lead to errors. Inspired by racetrack memory array architecture, the authors propose a new channel model in which missing data is filled with erasures at the end of the racetrack. Channel capacity and symmetric information rate for the proposed channel, a double-stack erasure-filled (DSEF) channel, are derived. Since the DSEF channel is a quaternary-input septenary-output channel, constructing good error-correcting codes is not trivial. We decompose the DSEF channel into two binary-input ternary-output channels to overcome this difficulty. This decomposition allowed us to construct an adequate error-correction scheme using existing binary codes, which is a meaningful achievement in terms of implementation.