Special Section on VLSI Design and CAD Algorithms
Low-Power Embedded Processor Design Using Branch Direction
2009 Volume E92.A Issue 12 Pages 3180-3181
Details
2009 Volume E92.A Issue 12 Pages 3180-3181
This paper presents a wordline gating logic for reducing unnecessary BTB accesses. Partial bit of the branch predictor was simultaneously recorded in the middle of BTB to prevent further SRAM operation. Experimental results with embedded applications showed that the proposed mechanism reduces around 38% of BTB power consumption.
