SAR ADC Algorithm with Redundancy and Digital Error Correction

Tomohiko OGAWA; Haruo KOBAYASHI; Yosuke TAKAHASHI; Nobukazu TAKAI; Masao HOTTA; Hao SAN; Tatsuji MATSUURA; Akira ABE; Katsuyoshi YAGI; Toshihiko MORI

doi:10.1587/transfun.E93.A.415

Special Section on Analog Circuit Techniques and Related Topics

SAR ADC Algorithm with Redundancy and Digital Error Correction

Tomohiko OGAWA, Haruo KOBAYASHI, Yosuke TAKAHASHI, Nobukazu TAKAI, Masao HOTTA, Hao SAN, Tatsuji MATSUURA, Akira ABE, Katsuyoshi YAGI, Toshihiko MORI

Author information

Tomohiko OGAWA
Electronic Engineering Department, Graduate School of Engineering, Gunma University
Haruo KOBAYASHI
Electronic Engineering Department, Graduate School of Engineering, Gunma University
Yosuke TAKAHASHI
Electronic Engineering Department, Graduate School of Engineering, Gunma University
Nobukazu TAKAI
Electronic Engineering Department, Graduate School of Engineering, Gunma University
Masao HOTTA
Department of Information Network Engineering, Tokyo City University
Hao SAN
Department of Information Network Engineering, Tokyo City University
Tatsuji MATSUURA
Semiconductor Technology Academic Research Center (STARC)
Akira ABE
Semiconductor Technology Academic Research Center (STARC)
Katsuyoshi YAGI
Semiconductor Technology Academic Research Center (STARC)
Toshihiko MORI
Semiconductor Technology Academic Research Center (STARC)

Keywords: SAR ADC, digital error correction, non-binary, redundancy

JOURNAL RESTRICTED ACCESS

2010 Volume E93.A Issue 2 Pages 415-423

DOI https://doi.org/10.1587/transfun.E93.A.415

Details

Abstract

This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC—because the latter must wait for the settling time of the DAC inside the SAR ADC.

Corresponding author

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