IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Analog Circuit Techniques and Related Topics
The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique
Shoichi HARARui MURAKAMIKenichi OKADAAkira MATSUZAWA
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Keywords: CMOS, VCO, divider, inductor
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2010 Volume E93.A Issue 2 Pages 424-430

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Abstract

The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -187.0dBc/Hz of FoM, can be extended from 6.5-12.5GHz to 1.5-12.5GHz. The proposed multiple-divide technique can provide a lower phase-noise, lower power consumption, smaller layout area of LC-VCO.

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© 2010 The Institute of Electronics, Information and Communication Engineers
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