The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (V_G=V_D). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.