Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS

Akira TSUCHIYA; Akitaka HIRATSUKA; Kenji TANAKA; Hiroyuki FUKUYAMA; Naoki MIURA; Hideyuki NOSAKA; Hidetoshi ONODERA

doi:10.1587/transele.2019CTP0008

Special Section on Analog Circuits and Their Application Technologies

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm² Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS

Akira TSUCHIYA, Akitaka HIRATSUKA, Kenji TANAKA, Hiroyuki FUKUYAMA, Naoki MIURA, Hideyuki NOSAKA, Hidetoshi ONODERA

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Keywords: optical communication, transimpedance amplifier, inductive peaking, on-chip inductor

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2020 Volume E103.C Issue 10 Pages 489-496

DOI https://doi.org/10.1587/transele.2019CTP0008

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Abstract

This paper presents a design of CMOS transimpedance amplifier (TIA) and peaking inductor for high speed, low power and small area. To realize high density integration of optical I/O, area reduction is an important figure as well as bandwidth, power and so on. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Multi-layered on-chip inductors are designed for area-effective inductive peaking. A 5-stage INV-TIA with 3 peaking inductors is fabricated in a 65-nm CMOS. By using multi-layered inductors, 0.02 mm² area is achieved. Measurement results show 45 Gb/s operation with 49 dBΩ transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency.

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