A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components

Yuncheng ZHANG; Bangan LIU; Teruki SOMEYA; Rui WU; Junjun QIU; Atsushi SHIRANE; Kenichi OKADA

doi:10.1587/transele.2021CDP0003

Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology

A 0.37mm² Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components

Yuncheng ZHANG, Bangan LIU, Teruki SOMEYA, Rui WU, Junjun QIU, Atsushi SHIRANE, Kenichi OKADA

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Keywords: receiver, area-efficient, impedance matching, dynamic range, mixer-first, low-power, wireless, Sub-GHz, IoT, 5G, CMOS

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2022 Volume E105.C Issue 7 Pages 334-342

DOI https://doi.org/10.1587/transele.2021CDP0003

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Abstract

This paper presents a fully integrated yet compact receiver front-end for Sub-GHz applications such as Internet-of-Things (IoT). The low noise amplifier (LNA) matching network leverages an inductance boosting technique. A relatively small on-chip inductor with a compact area achieves impedance matching in such a low frequency. Moreover, a passive-mixer-first mode bypasses the LNA to extend the receiver dynamic-range. The passive mixer provides matching to the 50Ω antenna interface to eliminate the need for additional passive components. Therefore, the receiver can be fully-integrated without any off-chip matching components. The flipped-voltage-follower (FVF) cell is adopted in the low pass filter (LPF) and the variable gain amplifier (VGA) for its high linearity and low power consumption. Fabricated in 65nm LP CMOS process, the proposed receiver front-end occupies 0.37mm² core area, with a tolerable input power ranging from -91.5dBm to -1dBm for 500kbps GMSK signal at 924MHz frequency. The power consumption is 1mW power under a 1.2V supply.

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