A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display

Ho-Seong KIM; Pil-Ho LEE; Jin-Wook HAN; Seung-Hun SHIN; Seung-Wuk BAEK; Doo-Ill PARK; Yongkyu SEO; Young-Chan JANG

doi:10.1587/transele.E100.C.1035

Special Section on Electronic Displays

A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display

Ho-Seong KIM, Pil-Ho LEE, Jin-Wook HAN, Seung-Hun SHIN, Seung-Wuk BAEK, Doo-Ill PARK, Yongkyu SEO, Young-Chan JANG

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Keywords: transmitter bridge chip, MIPI D-PHY, DSI, FPGA-based frame generator, phase-locked loop

JOURNAL RESTRICTED ACCESS

2017 Volume E100.C Issue 11 Pages 1035-1038

DOI https://doi.org/10.1587/transele.E100.C.1035

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Abstract

A 10 Gbps transmitter bridge chip including four data lanes, which increases the bandwidth using an 8-to-1 serialization, is proposed for a field-programmable gate array (FPGA)-based frame generator to support the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) display serial interface (DSI).

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