IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Regular Section
Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems
Jaeyong CHUNGWoochul KANG
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2017 Volume E100.C Issue 11 Pages 1073-1076

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Abstract

Massive amounts of computation involved in real-time evaluation of deep neural networks pose a serious challenge in battery-powered systems, and neuromorphic systems specialized in neural networks have been developed. This paper first shows the portion of active neurons at a time dwindles as going toward the output layer in recent large-scale deep convolutional neural networks. Spike-based, asynchronous neuromorphic systems take advantage of the sparse activation and reduce dynamic power consumption, while synchronous systems may waste much dynamic power even for the sparse activation due to clocks. We thus propose a clock gating-based dynamic power reduction method that exploits the sparse activation for synchronous neuromorphic systems. We apply the proposed method to a building block of a recently proposed synchronous neuromorphic computing system and demonstrate up to 79% dynamic power saving at a negligible overhead.

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© 2017 The Institute of Electronics, Information and Communication Engineers
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