IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Analog Circuits and Their Application Technologies
32-Gbit/s CMOS Receivers in 300-GHz Band
Shinsuke HARA, Kosuke KATAYAMA, Kyoya TAKANO, Ruibing DONG, Issei WATANABE, Norihiko SEKINE, Akifumi KASAMATSU, Takeshi YOSHIDA, Shuhei AMAKAWA, Minoru FUJISHIMA
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Keywords: Receiver, CMOS integrated circuits, terahertz, frequency conversion mixers, frequency multipliers, amplifiers, quadrature amplitude modulation
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2018 Volume E101.C Issue 7 Pages 464-471

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Abstract

This paper presents low-noise amplifier (LNA)-less 300-GHz CMOS receivers that operate above the NMOS unity-power-gain frequency, fmax. The receivers consist of a down-conversion mixer with a doubler- or tripler-last multiplier chain that upconverts an LO1/n signal into 300 GHz. The conversion gain of the receiver with the doubler-last multiplier is -19.5 dB and its noise figure, 3-dB bandwidth, and power consumption are 27 dB, 27 GHz, and 0.65 W, respectively. The conversion gain of the receiver with the tripler-last multiplier is -18 dB and its noise figure, 3-dB bandwidth, and power consumption are 25.5 dB, 33 GHz, and 0.41 W, respectively. The receivers achieve a wireless data rate of 32 Gb/s with 16QAM. This shows the potential of the moderate-fmax CMOS technology for ultrahigh-speed THz wireless communications.

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© 2018 The Institute of Electronics, Information and Communication Engineers
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