The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

Ki-Sang JUNG; Kang-Jik KIM; Young-Eun KIM; Jin-Gyun CHUNG; Ki-Hyun PYUN; Jong-Yeol LEE; Hang-Geun JEONG; Seong-Ik CHO

doi:10.1587/transele.E92.C.352

Regular Section

The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

Ki-Sang JUNG, Kang-Jik KIM, Young-Eun KIM, Jin-Gyun CHUNG, Ki-Hyun PYUN, Jong-Yeol LEE, Hang-Geun JEONG, Seong-Ik CHO

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Keywords: ROM, HG (Half Grouping), memory

JOURNAL RESTRICTED ACCESS

2009 Volume E92.C Issue 3 Pages 352-355

DOI https://doi.org/10.1587/transele.E92.C.352

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Abstract

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

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