A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache

Gi-Ho PARK; Jung-Wook PARK; Hoi-Jin LEE; Gunok JUNG; Sung-Bae PARK; Shin-Dug KIM

doi:10.1587/transele.E92.C.517

Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era

A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache

Gi-Ho PARK, Jung-Wook PARK, Hoi-Jin LEE, Gunok JUNG, Sung-Bae PARK, Shin-Dug KIM

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Keywords: way-enabling mechanism, branch information, embedded processor and low power instruction cache design

JOURNAL RESTRICTED ACCESS

2009 Volume E92.C Issue 4 Pages 517-521

DOI https://doi.org/10.1587/transele.E92.C.517

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Abstract

This paper presents a cache way enabling mechanism using branch target addresses. This mechanism uses branch prediction information to avoid the power consumption due to unnecessary cache way access by enabling only the cache way(s) that should be accessed. The proposed cache way enabling mechanism reduces the power consumption of the instruction cache by 63% without any performance degradation of the processor. An ARM1136 processor simulator and the Synopsys PrimeTime are used to perform the performance/power simulation and static timing analysis of the proposed mechanisms respectively.

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