Regular Section
A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS
2009 Volume E92.C Issue 4 Pages 589-591
Details
2009 Volume E92.C Issue 4 Pages 589-591
This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13µm CMOS process achieves 105MHz to 225MHz of clock frequency while consuming 4.2mW from 1.2V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8ps and 0.031% at 105MHz, respectively.
